Quantum computers – myths and reality
Blog
Quantum computers – myths and reality
The general public know more about quantum computers (QC) than silicon chips. Devs, the American science fiction thriller
https://lnkd.in/ddQSE6PK, provides good idea about quantum computers – both how they look and even what they may be capable of doing. QCs are all over the news – Google News features new QC story almost every new feed. The UK government and UK investors love QCs perhaps believing that in the future they may compensate for the UKs lack of advanced CMOS manufacturing capabilities. However, there are
and reality about quantum computers that should be clearly understood by the general public and by the politicians who make decisions about our science and technology future.
Myth No. 1: QCs will replace the classical (Von Neumann) computers.
Jack Krupansky addresses this myth in his article ‘What Can’t a Quantum Computer Compute?’ https://lnkd.in/dBE-cKME ‘Quantum computers offer some awesome features, but they lack most of the features of a general purpose Turing Machine which are offered by all classical computers.’ He lists 61 tasks that classical computers can and quantum computers cannot do. To start with: QC cannot compute PI to arbitrary large number of digits. Most importantly for me, QC cannot be used for solving partial differential equations – the backbone of modelling and simulation in all engineering disciplines including both CMOS and QC design.
So what are the ‘awesome’ QC features? According to Amit Katwala https://lnkd.in/dJm5X-65 ‘Quantum computers … let us do things that we couldn’t even have dreamed of without them’. This covers new algorithms for artificial intelligence (AI) applications, predicting uncertain complicated systems like the financial markets, drug discovery, and perhaps like in Devs, revealing the past future relations. From military and national security point of view the QC have the potential of cracking all encryption algorithms designed so far.
Myth No. 2. Silicon quantum chips can replace the ‘real’ (CMOS) chips.
Even if the development QC on a silicon chip is succesful, the replacement will be impossible, since QC cannot do most of the things that the silicon chip are currently doing in your mobile phones, laptops, workstations and data centres. And of course silicon QC can only work at very low temperature (close to milli-kelvin regime) – can you imagine carrying your mobile phone in a helium cryostat? By the way, perhaps more than 90% of the electronic contents of the present QCs are silicon chips.
Therefore, establishing and hopefully sustaining UK leadership in quantum computers is not a remedy for the UK lack of CMOS chip manufacturing capabilities. Clearly, we need to go back to the drawing board and figure out What Needs to be Done with CMOS in the UK.
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
Sausages or Chips?
Blog
Sausages or Chips?
To be honest I like them both. However, this is not a culinary post. This is about the importance of the collaboration between UK and EU in the area of CMOS technology and design through participation in EU projects. The UK’s exclusion from the Horizon programme will hamper our capabilities to rebuild CMOS technology and design expertise and the corresponding research, training and entrepreneurship.
The government’s pledge that a potential exclusion from Horizon can be compensated by increasing the amount of UK research funding will not work in the CMOS area. UK will have no access to the technology capabilities of IMEC, LETI, MINATEC, Fraunhofer and Tindal and to project partners like GLOBALFOUNDRIES, Infineon, ST Microelectronics, NXP, X-Fab, Bosh and others.
I would like to illustrate the role of the EU collaboration for the establishment, the growth and the success of my former TCAD company Gold Standard Simulation (GSS) by listing the role of the key EU projects in which we were involved:
ENIAC MODERN (2009) “MOdeling and DEsign of Reliable, process variation-aware
Nanoelectronic devices, circuits and systems” (ST Microelectronics (STM), Austria Microsystems, NXP Semiconductors, CEA-LETI, Synopsys and others). Although the UK decided not to fund this ENIAC project, I secured funding form Scottish Enterprise (SE) and EPSRC for the Glasgow University participation. GSS became a subcontractor creating the commercial version of the ‘atomistic’ TCAD simulator GARAND developed in my Device Modelling Group and licenced to GSS. GARAND was validated against state-of-the-art 40nm and 28nm CMOS measurements at STM.
TRAMS (2009) Terascale Reliable Adaptive Memory Systems (IMEC, Intel) played key role in the development of the GSS statistical compact model extractor Mystic and the statistical circuit simulation engine RandomSpice capable of predicting the impact of atomic scale variability on the yield of large SRAM arrays.
SUPERTHEME (2012) Circuit Stability Under Process Variability and Electro-Thermal-Mechanical Coupling (Frounhofer IISB, Austria Microsystems, ASML) played a key role in the development of the first TCAD based DTCO flow by GSS, including process induced and purely statistical variability.
Three Horizon projects SUPERAID7, CONNECT and REMINDER solidified the exit potential of GSS in 2016, enabling the development of the most advanced and comprehensive DTCO tool chain offered presently by Synopsys and used by the major advanced semiconductor manufacturers worldwide. As a result a 30 strong Synopsys R&D TCAD and DTCO centre was established in Glasgow.
Thus, the EU projects and collaborations provided GSS with crucial access to the knowledge and expertise of Intel, ST Microelectronics, NXP, Austria Microsystems, ASML, Synopsys, IMEC, CEA-LETI and others, enabling our success. GARAND, MYSTIC and RANDOM SPICE are now part of the Synopsys DTCO flow used by the major CMOS players worldwide. #semiconducto
If this subject is important to you please join the Silicon Futures network on LinkedIn.
The Quantum computer in Devs.
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
How many angels can dance on the top of a pin?
Press Release
How many angels can dance on the top of a pin?
How many angels can dance on the top of a pin?
(Or who is supporting the inverted electronics value chain pyramid?)
In the recent year even the general public started to realise that our inverted economy pyramid is balancing dangerously on the semiconductor industry. In this post I would like to focus on few facts.
In the figure below the data for the worldwide electronics value chain are from 2017, however the data for the wafer capacity are from 2020.
The worldwide GDP in 2017 was $81.2 trillion. $48.8 (60%) of this value was directly enabled by the semiconductor industry. Much of the rest of the GDP was most probably also heavily supported by the semiconductor industry.
The semiconductor manufacturers are supporting this top heavy inverted pyramid.
Clearly the support of the inverted pyramid from the East outweighs by far the support from the West. And in the middle between the West and the East is Russia…
For long year the UK focus has been at the top of the pyramid. Can you guess whose support of the inverted pyramid the hair thin line on the West represents? Actually the line should be so thin that it becomes invisible.
In strong wind situations the inverted pyramids have tendency of falling and crashing in the direction of less support.
#semiconductor #CMOS #microelectronics #electronics #economy
If this subject is important to you please join the Silicon Futures network on LinkedIn.
The Quantum computer in Devs.
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
Enabling Cryogenic Chip Design and the Scaling of Quantum Computers
Press Release
Enabling Cryogenic Chip Design and the Scaling of Quantum Computers
Multiple technologies have been demonstrated for generating and controlling qubits which are in the hearth of every quantum computer (QC). However, QCs have only been realised with a few dozen qubits, whereas to unlock their potential, they need to be scaled to thousands or even millions of qubits.
A QC needs control electronics to manipulate and read out from the qubit array, and to store and process the resulting data. Current implementations typically involve a qubit array chip located in a cryostat, with multiple coaxial cables running to banks of highDprecision roomDtemperature control electronics. This represents a major barrier to scaling because it’s impractical to run thousands of cables into cryostats, and the long cables introduce delays in signal transmission.
In principle, this integration problem can be solved using conventional silicon CMOS fabrication technology bringing the controlling and data processing CMOS chips closer to the qubits in the cryostats. However, existing integrated circuit design methodologies are only validated at temperatures close to room temperature (typically in the range -40oC to +125C), whereas qubit arrays operate at significantly lower temperatures. At such low temperatures commercial process design kits (PDKs) enabling the chip design and verification are not available which currently renders the cryogenic chip design practically impossible. Simultaneously semiconductors exhibit significantly different electronic characteristics at cryogenic temperatures, and the conventional CMOS IP and chip design solutions may not work as intended.
With decades of experience in lowDpower electronics design and simulation, Semiwise is now creating the necessary IP, knowDhow and methodology providing the muchDneeded cryogenic PDKs and enabling the design CMOS circuits optimised for QC applications and operating at cryogenic temperatures but manufactured using conventional foundries. Based on this technology the company will be offering services to recenter the standard foundry process design kits (PDKs) for allowing proper analogue and digital design at cryogenic temperatures. This will minimize the excess heat generated thereby easing the scalability challenges for large quantum computers.
“We are excited to become part of the QC revolution by providing for our customers with the much needed cryogenic PDKs and enabling cryogenic chip design and IP generation, enabling the QC scaling” commented the CEO of Semiwise, Professor Asenov.
About Semiwise: SemiWise (https://www.semiconductorwise.com/) develops innovative lowDpower CMOS transistorDlevel IP that improves performance and variability, and drastically reduces power consumption. SemiWise also offers simulation services and consulting to the semiconductor industry including fables, IEDM and foundry players. The CEO of Semiwise, Professor Asenov was the founder of Gold Standard Simulations (GSS), a 2010 startup from the University of Glasgow which developed the first TCAD based Design-Technology Co-Optimisation (DTCO) tool chain. After the acquisition of GSS by Synopsys in 2016 the TCADDtoDSpice technology originally developed by GSS is now part of the Synopsys TCAD offering in the so called TCAD toDSpice flow https://www.synopsys.com/silicon/tcad.html. This technology will be used in the Cryogenic PDK re-centering.
Contacts: asen.asenov@glasgow.ac.uk, +44 07523 293 782
Related Press Releases:
https://www.embedded.com/cryo-cmos-ip-enables-qubit-control-chips-at-cryogenic-temperatures/
https://www.eenewseurope.com/news/surecore-expands-control-logic-quantum-computing?fnid=140205/
Note: Professor Asenov is also a Director of Surecore.
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
£6.5M Innovate UK grant to develop cryogenic CMOS IP
Press Release
£6.5M Innovate UK grant to develop cryogenic CMOS IP
sureCore-led consortium wins £6.5M Innovate UK grant to develop cryogenic CMOS IP to accelerate Quantum Computing scalability
Innovate UK has awarded a grant of £6.5 million to a seven-member consortium led by sureCore with a remit to jointly develop advanced cryogenic semiconductor IP. This will dramatically accelerate the growth of the Quantum Computing (QC) industry by reducing the constrains associated with interconnects thus enabling efficient qubit/system scaling. The architecture of Quantum Computers combined with specialist algorithms have the power to transform computing efficiency to address problems in disciplines spanning fundamental science, pharmaceuticals, finance, logistics and AI.
Most leading quantum computing platforms utilise qubits or components that operate at cryogenic temperatures. The key challenge for these platforms is the lack of availability of suitable control circuitry capable of operating at the cryogenic temperatures needed to manage qubits operation. Currently the control circuitry is located remotely from the qubits and connected by expensive and bulky cabling in order to avoid the temperature extremes needed by the qubits. The amount of cabling required for all the qubits presents a fundamental barrier to QC scaling aside from the inherent latency impact.
The obvious solution is to co-locate the control electronics with the qubits in the cryostat but this means that both must be kept at ultra-low temperatures; in some implementations down to near absolute zero. However, not only is space extremely limited in the cryostat, necessitating the miniaturisation of the control circuity, but the modern semiconductors that make up these chips are only qualified to work down to -40° C. As the temperature is reduced close to absolute zero, the operating characteristics of the transistors change markedly. The aim of this project is to essentially understand and model this change in behaviour and then design a portfolio of CryoCMOS IP to enable the creation of custom chips that can interface to the qubits at cryogenic temperatures and support controller functionality.
A number of leading international technology companies are working on this for their own proprietary use. The UK has many smaller and start-up companies working in or associated with QC that would benefit enormously if a suite of CryoCMOS IP was available to license in much the same way as standard semiconductor IP licensing models work.
The consortium consists of the complete ecosystem of companies to provide the core competencies required to rapidly develop this cryo-tolerant IP. This would then be availableunder license for companies to create their own Cryo-CMOS chip solutions using it, turbo charging them with a competitive edge in the world of Quantum Computing.
The first step is accurately modelling how transistors work at these temperatures. This is being done by SemiWise and the QC research group at the University of Glasgow. Synopsys uses the data generated to refine its TCAD tools. A combination of measurements and simulation data will be used by SemiWise to re-centre the foundry PDK for cryogenic temperatures and to enable the cryogenic circuit design. As memory plays a key role in the electronics, this aspect is handled by sureCore, which is leading the project and whose expertise at keeping chip power consumption low is vital to ensure that waste heat is kept to a minimum so it does not heat the chamber. Chamber expertise is provided by Oxford Instruments which manufactures cryogenic systems. Lastly, Universal Quantum and SEEQC represent end user needs and will determine what IP blocks the project will need to create for the Cryo-CMOS chips. Test chips will be characterised at the cryo temperatures to further refine and validate the models and IP.
There are a large number of QC companies starting up in the UK. This project will help to make cryo-IP available to all of them so that they will be fast tracked in the race to provide QC solutions enabling the UK to be seen as a centre of competence for QC. By working as a team, the project expects to be able to achieve results in less than three years rather than the many years it would take working as individuals.
Oxford Instruments Nanotechnology Tools Limited https://nanoscience.oxinst.com/
Matt Martin, Director of Engineering at Oxford Instruments NanoScience, said: “Oxford Instruments is excited to be supplying its leading ultra-low temperature environmental know-how to support the Consortium’s chip characterisation requirements for the Cryo-CMOS IP. This is an important step in the commercial scale-up of quantum computing and the collaboration that needs to happen to secure ongoing UK quantum innovation and leadership.”
SEEQC UK Limited www.seeqc.com
Matthew Hutchins, CPO and co-founder at SEEQC, said: “Cryogenic logic is at the core of SEEQC’s unique quantum computing platform. This project provides an exciting opportunity to incorporate Cryo-CMOS into our chip-based, all-digital, Single Flux Quantum (SFQ) quantum architecture that can operate at the same temperatures as qubits and provides an advantageous interface for Cryo-CMOS. We look forward to working with the world-leading teams in this consortium to realise this goal.”
SemiWise Limited www.semiwise.uk
Professor Asen Asenov, CEO, said “SemiWise is delighted to play a key role in this project, delivering the cryogenic version of the foundry PDK and enabling the SRAM and, indeed, general circuit design at cryogenic temperatures. We believe that this will deliver a significant competitive advantage to the rest of the consortium partners.”
sureCore www.sure-core.com
Paul Wells, sureCore’s CEO, said: “We are proud to lead this project. It is vital to the success of this project that the Cryo-CMOS produces as little heat as possible. Heat comes from the power usage in the chip and we have perfected several ways to cut power consumption in the memory components of chips by up to 50%. As these QCs will be doing intense
computations, there will be huge demand for memory so the savings in power and hence heat will be critical to the operational success of the cryo control chips.”
Media contact Nigel Robson, Vortex PR. nigel@vortexpr.com +44 1481 233080
Synopsys www.synopsys.com/tcad
Victor Moroz, Synopsys Fellow, said “As a world-leading provider of Electronic Design Automation (EDA) solutions, Synopsys is committed to enabling our customers to explore and optimise the Cryo-CMOS circuits which will be a key facilitator for a wide-range of quantum technologies. Our Sentaurus TCAD (Technology Computer Aided Design) framework and TCAD to SPICE tools will enable design technology co-optimisation for Cryo-CMOS so that optimal performance-power-area-yield can be achieved in this new application area. We are excited to work with the diverse consortium of industrial and academic experts assembled in this project and feed the learnings into our existing toolchains so that they can be effectively utilised by our customers and partners.”
Universal Quantum Limited www.universalquantum.com
Adam Glibbery, IC Design Lead at Universal Quantum, said: “This consortium enables us to gain vital knowledge in low-temperature electronics, streamline our ASIC development work and accelerate our development roadmap as we work towards building the world’s first million-qubit quantum computer. Our unique quantum computer design does not require cooling to near 0° K nor need complex laser technology to control our trapped-ion qubits. This completely different approach to modularity uses electric field links and silicon technology to form an architecture that truly scales for commercial applications.”
Media contact Gemma Church, Universal Quantum, media@universalquantum.com +44 7967 565080.
University of Glasgow https://www.gla.ac.uk/
Professor Martin Weides, Professor of Quantum Technologies at the University of Glasgow, said: “University of Glasgow is an internationally recognised centre of excellence in quantum technology, from fundamental understanding through to translating world-changing technologies to industry. Our Centre for Quantum Technology, https://www.gla.ac.uk/research/az/quantumtechnology/, plays a fundamental role in the UK National Quantum Technology Programme. We’re delighted to working with our consortium partners to deliver Cryo-CMOS design and implementation for two quantum computing platforms and to train the next generation of researchers in materials, cryogenics, and electronics for quantum.”
Media contact Ross Barker, ross.barker@glasgow.ac.uk, Communications Manager, External Relation
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
The Semiwise’s Flat Field Transistor enables the continuation of DRAM scaling
Press Release
The Semiwise’s Flat Field Transistor enables the continuation of DRAM scaling
Although the DRAM cell transistors have undergone a dramatic revolution from recess gate to saddle FinFET, for cost reasons, the DRAM sense amplifiers and periphery continue to be manufactured using conventional bulk MOSFETs.
However, with the relentless scaling of the DRAM cell the margins of the sense amplifier (SA) dramatically decrease. The statistical variability (mismatch) of the bulk MOSFETs is the main factor eroding the SA margins. The addition of offset compensation circuits to the SA, adopted by most of the DRAM manufacturers, increases the SA related ‘dark’ area on the DRAM chips, further eroding the DRAM scaling. Recently Hynix has introduced recess gate (RG) SA transistors to tackle the DRAM SA statistical variability problem at increased manufacturing complexity and costs, and reduced performance.
Fig. 1 Comparison between the Hynix RG transistor and the Semiwise FFT
The FFT developed by Semiwise can deliver more than 50% reduction of the statistical variability compared to bulk MOSFETs with identical dimensions. This is complemented by 30% performance increase and 5% reduction of the manufacturing costs compared to the equivalent bulk CMOS technology transistors. More details about the FFT technology and performance are available at:
https://www.semiconductorwise.com/flat-field-transistor-technology
The advantages of the FFT can be sustained down to 22nm bulk CMOS offering long-term DRAM scaling solution. The Semiwise analysis shows that at 22nm bulk CMOS, the FFT delivers more than 50% reduction in the SA offset variability. This can be translated to more than 4 time reduction in the FFT SA area compared to the bulk MOSFET SA at identical offset variability distributions.
The CEO of Semiwise Prof. Asenov commented: “In the last 20 years I have been focusing my attention to the modeling and simulation of statistical variability in contemporary and future CMOS technologies. Simulation tools developed in my research group and former company, Gold Standard Simulations, are now in the heart of the Synopsys variability aware Design Technology Co-Optimisation (DTCO) flow. I am delighted that the use of these technology and tools has enabled Semiwise to develop the FFT technology that can revolutionizes the DRAM scaling.”
About Semiwise: Semiwise (https://www.semiconductorwise.com/) develops innovative low-power CMOS transistor-level IP that improves performance and variability, and drastically reduces power consumption. Semiwise also offers simulation services and consulting to the semiconductor industry including fabless, IEDM and foundry players. The CEO of Semiwise, Professor Asenov was the founder of Gold Standard Simulations (GSS), a 2010 start-up from the University of Glasgow which developed the first TCAD based Design-Technology Co Optimisation (DTCO) tool chain. After the acquisition of GSS by Synopsys in 2016 the TCAD-to-Spice technology originally developed by GSS is now part of the Synopsys TCAD offering in the so called TCAD-to-Spice flow https://www.synopsys.com/silicon/tcad.html. This technology was used in the development of the FFT.
Contacts: asen.asenov@glasgow.ac.uk, +44 07523 293 782
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
Semiwise Led Consortium Wins £354K Grant
Press Release
Semiwise Led Consortium Wins £354K Grant
Innovate UK has awarded a grant of £354,982 to a consortium led by SemiWise with the remit to develop and deliver training courses for power electronic devices manufacturing companies in the UK. This funding will accelerate the growth of the power electronics industry by addressing the acute training and recruitment shortage in the semiconductor sector.
The project, called “Virtual Manufacturing Based Power Electronics Design and Manufacturing Training Courses,” was submitted in response to the Innovate UK call, “Driving the Electric Revolution – Building Talent for the Future 2.”
The power electronic industry in the UK is a key element of the Power Electronics, Motors and Drives (PEMD) manufacturing supply chain. The courses to be developed will take on an innovative virtual approach utilizing industry-leading Synopsys Sentaurus™ Technology Computer Aided Design (TCAD) tools and the Synopsys Design Technology Co-Optimization (DTCO) solution for power electronics. This allows hands-on training—including face-to-face, Zoom and on-demand web-based delivery— without prohibitively expensive manufacturing training facilities. The courses will cover silicon (Si), silicon carbide (SiC) and gallium nitride (GaN) power electronics devices, which are all of interest to UK power electronics manufacturers.
The leading organization SemiWise will oversee the course development and delivery. The CEO of SemiWise, Professor Asen Asenov, who is also the James Watt Professor of Electrical Engineering at Glasgow University, has more than 40 years of experience in the semiconductor industry and academia. In the last 30 years he has developed and delivered most of the semiconductor and power electronics courses at Glasgow University.
“SemiWise is delighted to play a key role in this project, developing the courses and the virtual manufacturing-based laboratories and delivering the training. The project will strongly benefit from the expertise of Synopsys in this field as well as by the use of the industry-leading Synopsys Sentaurus™ TCAD and DTCO solutions,” said Asenov. . “We believe that this project will deliver significant competitive advantage to the power electronics industry in the UK.”
Jillian Hughes, NMI network director, is delighted to be working with SemiWise, Synopsys and the industry on a course that is welcomed by its members. “This will help address some of the skills issues that we are facing by training new graduates, and by upskilling and reskilling existing employees, in an industry that is finding it difficult to attract new and experienced talent,” said Hughes. “This is a course which is unique and can be tailored to individual needs, as it is not taught in any university program, and I am excited to be part of this.”
This work was funded by Driving the Electric Revolution, an ISCF Challenge delivered by UK Research and Innovation.
About SemiWise: SemiWise (https://www.semiconductorwise.com/) develops innovative low-power CMOS transistor-level IP that improves performance and variability, and drastically reduces power consumption. SemiWise also offers simulation services and consulting to the semiconductor industry including fables, IEDM and foundry players. The CEO of SemiWise, Professor Asenov was the founder of Gold Standard Simulations (GSS), a 2010 start-up from the University of Glasgow which developed the first TCAD based Design-Technology Co Optimisation (DTCO) tool chain. After the acquisition of GSS by Synopsys in 2016 the TCAD-to-Spice technology originally developed by GSS is now part of the Synopsys TCAD offering in the so called TCAD-to-Spice flow and continues to be developed by the Synopsys R&D division in Glasgow: https://www.synopsys.com/silicon/tcad.html.
Semiwise contact: asen.asenov@glasgow.ac.uk, +44 07523 293 782
About TechWorks: Techworkshub Ltd is a not-for-profit industry association consisting of member companies across the UK Deep Tech scene. We build collaborative networks to support the UK Deep Tech Sector, forming adjacent, connected communities which represent major players in technology industries to create vision and scale, driving profitable growth for UK Deeptech business. Originally conceived as the National Microelectronics Institute (NMI) in 1996, Techworks now consists of 270 member companies across four collaborative networks where semiconductor design, IP creation, manufacturing and associated supply chain are represented. NMI, a network of Techworkshub supports the established Semiconductor Manufacturing and supply chain communities with activities that encourage innovation, communication and collaboration
NMI contact: jillian.hughes@techworks.org.uk
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
Power Electronic Device Training Courses
Press Release
Power Electronic Device Training Courses
Power Electronic Device Training Courses Like Never Before
Power electronic devices are in the heart of all power converter applications: power supplies, motors and drives, electric cars, solar panels, wind turbines. Better power electronic devices with as little power loses as possible determine the milage of the electric cars and the efficiency of the renewable energy sources. The projected growth of the power electronics semiconductor industry exceeds the projected growth for the rest of the semiconductor industry. The current downturn of the semiconductor industry has not affected much the power electronics device manufacturers.
However, the design and the optimisation of power electronics devices are in many respects more complicated than the design of the metal oxide semiconductor (MOS) transistors in CMOS chips. According to the CEO of Semiwise Professor Asenov “If you think that you know and understand power semiconductor devices, think again. The power electronics semiconductor devices are completely new world. Have you heard about conductivity modulation, reverse recovery, on state resistance, safe operating area? All these are essential for the design and the optimisation even of the simplest power electronics device – the silicon power PiN diode.”
In the framework of the Innovate UK funded project “Virtual Manufacturing Based Power Electronics Design and Manufacturing Training Courses,” in collaboration with NMI and Synopsys, we are developing power electronics device courses for the future. For the first time the courses are entirely based on simulations and illustrations using the Synopsys TCAD tools, which are not only perfectly suited for design and optimization of power electronics devices but essential for the corresponding teaching. The lectures in our power electronics course modules are complemented with TCAD laboratories using the industry leading TCAD simulator: Sentaurus Process and Device.
The figure on the right illustrates the Si PiN diode turn-on and turn-off transients responsible for a significant part of the power losses in every power converter. The attempt to switch the diode faster increases the power losses during the turn-on and turn-off transients. The power diode related converter losses can be significantly reduced by using SiC Schottky diodes.
If you would like to learn more, please visit the corresponding Semiwise web page: https://www.semiconductorwise.com/copy-of-trainig-ped
SemiWise develops innovative low-power CMOS transistor-level IP that improves performance and variability, and drastically reduces power consumption. SemiWise also offers simulation services, consulting and training courses to the semiconductor industry including fabless, IEDM and foundry players. The CEO of SemiWise, Professor Asenov was the founder of Gold Standard Simulations (GSS), a 2010 start-up from the University of Glasgow which developed the first TCAD based Design-Technology Co Optimisation (DTCO) tool chain. After the acquisition of GSS by Synopsys in 2016, the TCAD-to-Spice technology originally developed by GSS is now part of the Synopsys TCAD offering in the so called TCAD-to-Spice flow and continues to be developed by the Synopsys R&D division in Glasgow: https://www.synopsys.com/silicon/tcad.html.
www.semiconductorwise.com asen.asenov@glasgow.ac.uk +44 07523 293 782
Flat Field Transistor Technology
Channel Last Transistor Technology
Patents
Virtual Reality Semiconductor Training Lab
Press Release
Virtual Reality Semiconductor Training Lab
A consortium led by Semiwise wins an Innovate UK grant to develop Virtual Reality Semiconductor Training Fab.
Building an advanced semiconductor fabrication facility typically incurs a cost ranging from $10 billion to $20 billion. The expense of a single deep EUV stepper, at $500 million, exceeds that of an Airbus A380. Consequently, the challenge arises of how to train individuals to work within a costly semiconductor fabrication facility without imposing a burden on vital resources within an existing facility or constructing a new educational one. The solution mirrors the approach employed in training pilots to operate an Airbus A380: the use of virtual reality simulators.
Semiwise, in partnership with The National Microelectronics Institute (a division of Techworks) and Pragmatic Semiconductor Limited, secured a grant from Innovate UK to develop a Virtual Reality Semiconductor Fabrication Training Facility (VRSFT). Synopsys and Denova are subcontracted for this venture. Through virtual reality (VR), we intend to craft an immersive VR model of a contemporary fabrication facility featuring lifelike representations of the equipment, which can be operated analogously to flight simulators.
Upon initial evaluation, given the available funding of £500,000, this project may seem overly ambitious. Developing the Airbus A380 flight simulator required several years and approximately €20 million in expenditure. Fortunately, the Technology Computer-Aided Design (TCAD) process simulation tool, “Sentaurus Process Explorer,” can simulate the operation of crucial equipment used in semiconductor device manufacturing. Synopsys will provide their Technology Computer Aided Design (TCAD) software and establish connections with key equipment manufacturers. This approach enables us to create an advanced training simulator without necessitating substantial initial capital investment and time allocation.
Professor Asenov, CEO of Semiwise, expressed his belief: “We consider this approach to be one of the most effective means of training and up-skilling engineers for work in the semiconductor industry. This initiative will propel the UK to the forefront of semiconductor education, as to the best of our knowledge no comparable program exists anywhere in the world.”
Charles Sturman, CEO of Techworks, emphasised the significance of the project: “This project constitutes a vital component in ensuring the success of the UK Semiconductor Initiative. The UK possesses the potential to emerge as a global leader in semiconductor R&D and training, owing to its world-renowned universities and robust academic presence.”
Clare Hodcroft, Vice President of People at Pragmatic Semiconductor, highlighted the potential global impact of virtual reality training: “As the sector innovates and develops new technology, like Pragmatic’s flexible integrated circuits, the global demand for skills will continue to grow. Virtual reality training has the potential to accelerate adoption of this technology, both in the UK and worldwide.”
As reported by Electronics Weekly, the chip industry anticipates a need for over 1 million additional employees by 2030. With training costs ranging from $20,000 to $50,000 per employee, this forecast translates to a training revenue potential ranging from $20 billion to $50 billion for universities and training institutions.
The commencement of this project coincides with Semiwise’s participation in the ARM-led Semiconductor Education Alliance.
This Virtual Manufacturing Based Power Electronics Design and Manufacturing Training Courses project was supported by the UKRI’s Driving the Electric Revolution Challenge that is delivered by Innovate UK challenge fund who awarded funding through the Building Talent for the Future 2 opportunity.
About Semiwise: SemiWise (https://www.semiconductorwise.com/) develops innovative low-power CMOS transistor-level IP that improves performance and variability, and drastically reduces power consumption. SemiWise also offers simulation services and consulting to the semiconductor industry including fables, IEDM and foundry players. The CEO of Semiwise, Professor Asenov was the founder of Gold Standard Simulations (GSS), a 2010 startup from the University of Glasgow which developed the first TCAD based Design- Technology Co Optimisation (DTCO) tool chain. After the acquisition of GSS by Synopsys in 2016 the TCAD-to-Spice technology originally developed by GSS is now part of the Synopsys TCAD offering in the so called TCAD-to-Spice flow and continues to be developed by the Synopsys R&D division in Glasgow
About NMI: The National Microelectronics Institute (NMI) in the UK is a leading trade association and industry organisation that plays a pivotal role in advancing the microelectronics sector. With a strong focus on innovation, collaboration, and advocacy, NMI brings together a diverse community of businesses, researchers, and professionals in the fields of microelectronics, semiconductor design, and electronics manufacturing. Through its extensive network and initiatives, NMI supports the growth and competitiveness of the UK’s electronics industry, fostering technological advancements and driving economic impact across a wide range of sectors, from healthcare to automotive and beyond: https://nmi.org.uk/.
About Pragmatic: Pragmatic is revolutionising semiconductor fabrication with ultra-low-cost, flexible integrated circuit (FlexIC) technology that makes it quick and easy to embed intelligence almost anywhere. FlexICs are thinner than a human hair and, invisibly embedded in objects, enable novel solutions that are simply not possible with conventional electronics. With rapid cycle times that substantially accelerate time to market, our foundry provides high-volume fabrication at a fraction of the cost of silicon, with a significantly lower environmental impact: https://www.pragmaticsemi.com/.
For further information please contact Prof Asen Asenov: mobile: 07532 293 782, e-mail: asen.asenov@glasgow.ac.uk,